1. Field of the Invention
The present invention relates to a chip scale package, and to a printed circuit board on which chip scale packages are to be mounted so as to become integrated. More particularly, the present invention relates to the design of the layout of external terminals of the chip scale package, and to the corresponding layout of terminals and signal line (wiring) patterns of a printed circuit board.
2. Description of the Related Art
To meet the recent demands for miniaturization and high-speed operation in chip-based technology, chip packages are becoming lighter, thinner, and smaller. Moreover, the features that pose the most limits on the operating speed of the chip are the electrical characteristics of the chip package. In particular, the electrical characteristics of pins for connecting a chip with an external device can greatly affect the operating speed of the chip package. Thus, various kinds of chip packages have been developed around the physical structure and arrangement of their pins.
A chip package that operates at a low speed has a lead frame, and a plurality of pins arranged in a single row at one side of the package. However, such an arrangement poses a limitation on the number of the pins that can be accommodated, the limitation becoming more severe the smaller the package. Moreover, such an arrangement of pins is not suitable for a chip package required to perform a high-speed operation because large amounts of inductance, parasitic capacitance, resistance and the like occur between a bonding pad and the lead frame of the chip package.
To overcome such limitations, a chip scale package (CSP) has been developed in which a plurality of pins (or balls) are arranged along a grid, i.e., two-dimensionally. Such a chip scale package has an advantage in that the electrical parasitic factor of the pins (balls) is less than that of a comparable package comprising a lead frame. Thus, chip scale packages can be made small and yet operate at a high speed.
FIG. 1A is a sectional view of a conventional chip scale package 10 known as a ball grid array (BGA) package. The BGA package 10 includes a semiconductor chip 13 which is electrically connected to I/O pins (solder balls)12. The chip 13 is supported on a printed circuit board (PCB) 11. The PCB 11 also serves to connect the chip 13 to the pins (balls) 12. A detailed description of BGA packages can be found in U.S. Pat. No. 6,041,495, the contents of which are hereby incorporated by reference.
FIG. 1B is a plan view of the pin (ball) layout of the conventional chip scale package 10. Basically, a plurality of the balls 12 are arranged regularly along a grid. When the chip scale package 10 constitutes a memory device, the balls 12 include balls dedicated, respectively, to transmit address and command signals, and to input or output data, and respective balls to be connected to ground and to a power source. In the figure, d1 represents the distance between two adjacent balls 12 along one direction X in the grid, and d2 represents the distance between two adjacent balls 12 along the other direction Y in the grid perpendicular to the first direction X.
A plurality of such chip scale packages are mounted on one surface of a printed circuit board (e.g., a mother board). The pins (balls) are spaced from one another by regular intervals d1, d2, and the pin (ball) lands of the printed circuit board that receive the pins (balls) of the chip scale package are thus also spaced from one another by regular intervals. As discussed in more detail below, only one signal line can be arranged between two adjacent pin (ball) lands. Consequently, all of the required signal lines can not be accommodated on the front surface of a printed circuit board to which the chip scale packages are mounted. Therefore, an additional wiring layer is required for facilitating signal lines, which layer contributes to the high production cost of the board using the chip scale package technology.
FIG. 2 is a plan view of such a printed circuit board on which a plurality of the chip scale packages are mounted. As shown in FIG. 2, eight chip scale packages 10-1 to 10-8 are mounted on the printed circuit board 100. A terminal circuit 14 is arranged to one side (to the left in the figure) of the first chip scale package 10-1. The terminal circuit 14 includes a plurality of pairs of a terminal resistor Rt and a terminal voltage Vt, which are connected in series with each other. The terminal circuit 14 is used to match the impedance of all of the signal lines common to the chip scale packages 10-1 to 10-8. Input/output terminals 16-1 and 16-2 allow signals to be input and output to and from the printed circuit board 100.
However, as was mentioned above, it is very difficult to accommodate all of the signal lines on the front surface of the printed circuit board 100 on which the chip scale packages 10 are mounted. This is because the balls 12 are disposed so close to one another that barely one signal line can pass therebetween. Therefore, most of the signal lines are provided on the other (lower) layers of the printed circuit board 100.
Hereinafter, a configuration of a conventional printed circuit board, having an eight-layered structure, will be described below with reference to FIGS. 3 to 9. These figures are plan views of each of the layers (except for the sixth layer) of the conventional printed circuit board, respectively.
As shown in FIG. 3, the first layer has eight chip scale package regions 10-1 to 10-8 on which the chip scale packages are to be mounted. Ball lands 18 are provided on each of the chip scale package regions 10-1 to 10-8 at locations corresponding to the balls 12 of the chip scale package 10 (see FIG. 1B) to be mounted thereon. A via hole 20 is provided adjacent each ball land 18 for facilitating an electrical connection between the ball lands 18 and signal lines on the lower layers of the printed circuit board. Although not shown, the input and output terminals 16-1 and 16-2 shown in FIG. 2 are connected as well through via holes 20 to signal lines on the lower layers of the printed circuit board.
As shown in FIG. 4, the second layer serves as a ground layer. Via holes 20 in the second layer which are depicted as triangles (for illustration only) serve as ground via holes. In particular, the xe2x80x9ctriangularxe2x80x9d via holes 20 are electrically connected with certain ones of the ball pads 18 on the first layer of the printed circuit board 100. Ground balls of the chip scale package 10 mounted on these ball pads are thus grounded via the triangular via holes 20.
As shown in FIG. 5, the third layer has a plurality of via holes 20 that are electrically connected to the corresponding via holes in the second layer 20, respectively. That is, the via holes 20 shown in FIGS. 3 and 4 are filled with a conductive material so that an electrical connection is provided between the respective layers of the printed circuit board.
Note, the via holes 20 located on one side of the chip scale package regions 10-1 to 10-8 (the upper portion as viewed in the figures) are first via holes dedicated to address and command signal lines, and the via holes 20 located on the other side of the chip scale package regions 10-1 to 10-8 are second via holes dedicated to data lines for inputting and outputting data. Reference numeral 22-1 designates the address and command signal lines connected with respective ones of the first via holes 20. The address and command signal lines 22-1 also pass between adjacent rows of the first via holes 20. The data lines 24-11 to 24-81 are connected to the second via holes 20, respectively. Although not shown, the address and command signal lines 22-1 and the data lines 24-11 to 24-81 are connected with corresponding ones of input and output terminals (e.g., the terminals 16-1 and 16-2 shown in FIG. 2).
All of the address and command signal lines and data lines can not be wired on the third layer of the printed circuit board 100 because each pair of adjacent via holes 20 allows only one line to pass therebetween. That is, only some of the address and command signal lines and only some of the data lines are formed on the third layer.
As shown in FIG. 6, the fourth layer includes via holes 20 that are connected with the via holes 20 of the third layer shown in FIG. 5. The fourth layer is the one at which the chip scale packages are connected to a power source. The xe2x80x9crectangularxe2x80x9d via holes 20 serve as power via holes. That is, the rectangular power via holes 20 in the fourth layer are connected with the corresponding via holes in the first to third layers, and are connected to lines emanating from a power source.
As shown in FIG. 7, the fifth layer includes via holes 20 that are connected with the via holes 20 of the fourth layer shown in FIG. 6. Similar to the third layer, the fifth layer includes some of the address and command signal lines 22-2 and some of the data lines 24-12 to 24-82. In other words, some of the wiring which can not be accommodated on the third layer is provided on the fifth layer.
The configuration of the sixth layer of the printed circuit board is the same as that of the second layer shown in FIG. 4. Thus, a separate illustration of the sixth layer is omitted for the sake of brevity, and reference is again made to FIG. 4. In the sixth layer, triangular via holes 20 are electrically connected with corresponding via holes of the first and second layers, the former of which receive the ground balls of the chip scale packages 10-1 to 10-8. Therefore, the chip scale packages 10-1 to 10-8 are grounded only through the ground balls. When designing the printed circuit board on which the chip scale package(s) is/are to be mounted, the ground layer and/or the power layer is/are typically interposed between the layers on which the address and command signal lines and the data lines are provided.
Next, as shown in FIG. 8, the seventh layer includes via holes 20 that are connected with the via holes 20 of the sixth layer shown in FIG. 7. Similar to the fifth layer, the seventh layer includes some of the address and command signal lines 22-3 and some of the data lines 24-13 to 24-83. In other words, the wiring which can not be accommodated on the third and fifth layers is provided on the seventh layer.
Finally, as shown in FIG. 9, the eighth layer includes via holes 20 that are connected with the via holes 20 on the seventh layer shown in FIG. 8.
In the eight-layered structure of the printed circuit board, as shown in FIGS. 3 to 9, each of the address and command signal lines is shared in common by the chip scale package regions 10-1 to 10-8, and, on the other hand, the data lines are not shared in common and instead transmit data to and from only one of the chip scale packages 10-1 to 10-8. In this configuration, even though some of the via holes 20 are not connected to any of the wiring, eight layers are nevertheless required. Further, if it was necessary to wire more or all of the via holes 20 on the chip scale package regions 10-1, than an eight-layer printed circuit board may prove to be insufficient, in which case an additional layer or layers would be required.
In response to the continuing demand for higher operating speeds, chip scale packages are designed with greater numbers of contact balls to facilitate transmission of numerous address and command signals at high input/output speeds. The printed circuit boards on which such a chip scale packages are to be mounted must have a correspondingly large number of signal lines. As such, as the number of contact balls of the chip scale package requiring a connection increases, the number of layers of the conventional circuit board must also increase. The conventional printed circuit board thus requires numerous interlayer wiring layers, leading to high production costs.
It is thus one object of the present invention to provide chip scale packages that allow the printed circuit board on which the chip scale packages are to be mounted to possess a minimal amount of layers for accommodating all of the external signal lines necessary for the chip scale packages.
In order to achieve this object, one aspect of the present invention provides a chip scale package having first and second sets of external signal terminals (pins/balls) arranged in rows and columns at respective sides of the bottom surface of the package, wherein the spacing between the rows and/or columns of the first set of signal terminals is greater than the spacing between the rows and/or columns of the second set of signal terminals. What is meant by the term xe2x80x9cthe spacingxe2x80x9d is the average distance between adjacent rows and columns, i.e., the average pitch of the spaced apart rows and the average pitch of the space apart columns.
The signal terminals of the first set are of the type that are used to transmit low frequency signals, such as address and command signals, that are intended to travel among a plurality of the chip scale packages via first signal lines of a printed circuit board (PCB) that are shared in common by such packages. On the other hand, the signal terminals of the second set are of the type that are intended to transmit high frequency signals, such as data signals, to/from the chip of only that package. That is, the PCB signal lines to be connected to the second set of terminals are not shared.
The spacing between the rows of the first set of signal terminals is preferably greater than the spacing between the rows of said second set of signal terminals so that a plurality of signal lines can be provided between the rows of the first set of signal terminals when the chip packages are mounted to the PCB. Also, the spacing between the columns of the second set of signal terminals is preferably less than the spacing between the columns of said first set of signal terminals so that a plurality of signal lines can be provided adjacent the set of signal terminals when the chip packages are mounted to the PCB. The design of the chip scale package thus facilitates the provision of more of the signal lines on a layer of the PCB than in the prior art. Thus, fewer additional layers are required to accommodate the remainder of the signal lines.
Likewise, it is another object of the present invention to provide a printed circuit board, on which chip scale packages are to be mounted, having an efficient arrangement of signal lines, whereby the number of layers of the printed circuit board is kept to a minimum.
To achieve this object, another aspect of the present invention provides a printed circuit board comprising a substrate having a plurality of linearly spaced-apart chip scale package regions, a first set of receiving terminals (lands) disposed at one side of each chip scale package region in a plurality of rows and columns, a second set of receiving terminals (lands) disposed at the other side of the chip scale package region also in a plurality of rows and columns, wherein the spacing between the rows of the first set of terminals is greater than the spacing between the rows of the second set of terminals, a first set of signal lines a plurality of which extend contiguously between each adjacent pair of rows of the first set of terminals in each of the chip scale package regions, and second signal lines connected to the receiving terminals of the second set in each chip scale package region.
The first signal lines are dedicated as address and command signal lines. Each of the signal lines of the first set is connected to a respective terminal constituting the adjacent pair of rows in each of the chip scale package regions. The number of first signal lines extending between each pair of adjacent rows of first set of receiving terminals, in each chip scale package region, is preferably equal to half the number of columns of the first set of receiving terminals in the chip scale package region.
The second signal lines are dedicated as data lines. Each of the second signal lines is connected to only one receiving terminal of the second set, in each chip scale package region.
Half of all of the required signal lines can be provided on the layer of the of the PCB at which the chip scale package regions are defined, and are preferably provided on the upper outer surface of the substrate of the PCB. The remainder of the signal lines can be provided all on another layer, such as on the lower outer surface, or layers.
Another object of the present invention is to provide an electronics module that is economical to produce. This object is achieved by the combination of the above-described printed circuit board and chip scale packages mounted thereto.
It is still another object of the present invention to provide a method of designing a printed circuit board of a module in which chip scale packages are integrated, which will minimize the number of layers to be produced for accommodating the signal lines used to integrate the chip scale packages.
To achieve this object, another aspect of the present invention provides a method of designing a printed circuit board. The method includes creating a chip scale package region layout to scale for one of the layers of the printed circuit board, determining the total number n of the first signal lines through which signals need to be transmitted along the printed circuit board among chip scale packages mounted over the chip scale package regions, respectively, and creating a receiving terminal layout of a plurality of first terminal locations (lands) in each chip scale package region by factoring the number n of required first signal lines into factors of c and r, arranging the first terminal locations in a number of rows equal to r in each chip scale package region, and in a number of columns equal to c in each chip scale package region, and spacing the rows from each other by intervals sufficient to allow at least c/2 of the first signal lines to be printed on the circuit board between adjacent rows of the terminals formed on the printed circuit board according to the receiving terminal layout.
A first signal line layout to scale is also created, representing locations at which the first signal lines are to be formed on the layer of the PCB at which the chip scale package regions are defined. The first signal line layout is created by laying out between each pair of adjacent rows of the first terminal locations, in each chip scale package region location, (at least) n/2 first signal line traces passing from one chip scale region location to the other and each of which traces is connected in each of the chip scale package regions with a respective one of the first terminal locations comprising the adjacent rows thereof.
A receiving terminal layout and a signal line layout are also created for the second signal lines.
A via hole layout is then created, representing the locations of via holes to be connected to respective ones of the first and second receiving terminals that are not designated for connection to a signal line on the layer of the PCB at which the chip scale package regions are defined.
An additional set(s) of signal line layouts is created for another layer(s) of the PCB. The via holes represented by the via hole layout will extend to this/these layer/layers for connection to the signal lines represented by the additional set(s) of signal line layouts.
As described hereinabove, according to the present invention, the number of common signal lines on a layer(s) of the printed circuit board is increased so that the total number of layers of the printed circuit board required to accommodate all of the signal lines can be decreased. Thus, the production cost of the PCB can be kept low.